四位十進制數(shù)字頻率計VHDL，DE1開發(fā)板驗證

名稱：四位十進制頻率計VHDL，DE1開發(fā)板驗證（代碼在文末付費下載）

軟件：Quartus

語言：VHDL

要求：

數(shù)字頻率計設計要求：

1、四位十進制數(shù)字顯示的數(shù)學式頻率計,其頻率測量范圍為10~9999khz,測量單位為kHz。

2、要求量程能夠轉換。即測幾十到幾百千(kHz)時,有小數(shù)點顯示,前者顯示小數(shù)點后2位,后者顯示小數(shù)點后1位。

3、當輸入的信號小于10kHz時,輸出顯示全0;當輸入的信號大于9999kHz時,輸出顯示全H。

本代碼已在DE1開發(fā)板驗證，開發(fā)板照片如下：

部分代碼展示

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--計數(shù)器模塊
ENTITY?counter?IS
???PORT?(
??????signal_in??:?IN?STD_LOGIC;--被測信號
??????en?????????:?IN?STD_LOGIC;--1mS閘門信號
??????rst????????:?IN?STD_LOGIC;--復位
??????alarm??????:?OUT?STD_LOGIC;--報警
??????number?????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)--頻率值
???);
END?counter;
ARCHITECTURE?trans?OF?counter?IS
???SIGNAL?num_0?:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";
???SIGNAL?num_1?:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";
???SIGNAL?num_2?:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";
???SIGNAL?num_3?:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";
BEGIN
???
???number?<=?(num_3?&?num_2?&?num_1?&?num_0);--單位Hz
???
???--計數(shù),計數(shù)1s內的信號周期數(shù)，計數(shù)值就是頻率值
???PROCESS?(signal_in,?rst)
???BEGIN
??????IF?(rst?=?'1')?THEN
?????????num_0?<=?"0000";
?????????num_1?<=?"0000";
?????????num_2?<=?"0000";
?????????num_3?<=?"0000";
?????????alarm?<=?'0';
??????ELSIF?(signal_in'EVENT?AND?signal_in?=?'1')?THEN
?????????IF?(en?=?'1')?THEN--計數(shù)，低位都是9，則高位加1，低位清零，例如加到999，則變?yōu)?000
????????????IF?(num_3?=?"1001"?AND?num_2?=?"1001"?AND?num_1?=?"1001"?AND?num_0?=?"1001")?THEN
???????????????num_0?<=?"0000";
???????????????num_1?<=?"0000";
???????????????num_2?<=?"0000";
???????????????num_3?<=?"0000";
???????????????alarm?<=?'1';--報警
????????????ELSIF?(num_2?=?"1001"?AND?num_1?=?"1001"?AND?num_0?=?"1001")?THEN
???????????????num_0?<=?"0000";
???????????????num_1?<=?"0000";
???????????????num_2?<=?"0000";
???????????????num_3?<=?num_3?+?"0001";--低位為9，則高位加1，低位清零
???????????????alarm?<=?'0';
????????????ELSIF?(num_1?=?"1001"?AND?num_0?=?"1001")?THEN
???????????????num_0?<=?"0000";
???????????????num_1?<=?"0000";
???????????????num_2?<=?num_2?+?"0001";--低位為9，則高位加1，低位清零
???????????????num_3?<=?num_3;
???????????????alarm?<=?'0';
????????????ELSIF?(num_0?=?"1001")?THEN
???????????????num_0?<=?"0000";
???????????????num_1?<=?num_1?+?"0001";--低位為9，則高位加1，低位清零
???????????????num_2?<=?num_2;
???????????????num_3?<=?num_3;
???????????????alarm?<=?'0';
????????????ELSE
???????????????num_0?<=?num_0?+?"0001";--低位加1
???????????????num_1?<=?num_1;
???????????????num_2?<=?num_2;
???????????????num_3?<=?num_3;
???????????????alarm?<=?'0';
????????????END?IF;
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???
END?trans;

設計文檔(文檔點擊可下載)：

1. 工程文件

2. 程序文件

3. 程序編譯

4. 管腳分配

5. 仿真圖

整體仿真圖

計數(shù)器模塊

鎖存器模塊

控制模塊

產生閘門信號，清零信號，鎖存信號

數(shù)碼管顯示模塊

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=185