定時器的設(shè)計Verilog代碼Quartus仿真

名稱：定時器的設(shè)計Verilog代碼Quartus仿真

軟件：Quartus

語言：Verilog

代碼功能：

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖

5. Testbench

6. 仿真圖

整體仿真圖

分頻模塊

設(shè)置當前模式模塊

計時模塊

響鈴模塊

部分代碼展示:

`timescale?1?ns/?1?ns
module?timmer_tb();
reg?CLK;
reg?HRS;
reg?MINS;
reg?RST;
reg?SET_ALARM;
reg?SET_TIME;
reg?TOGGLE_SWITCH;
//?wires???????????????????????????????????????????????
wire?SPEAKER_OUT;
wire?[7:0]??hour_alarm;
wire?[7:0]??hour_time;
wire?[7:0]??minute_alarm;
wire?[7:0]??minute_time;
wire?[7:0]??second_alarm;
wire?[7:0]??second_time;
//?assign?statements?(if?any)??????????????????????????
timmer?i1?(
//?port?map?-?connection?between?master?ports?and?signals/registers???
.CLK(CLK),
.HRS(HRS),
.MINS(MINS),
.RST(RST),
.SET_ALARM(SET_ALARM),
.SET_TIME(SET_TIME),
.SPEAKER_OUT(SPEAKER_OUT),
.TOGGLE_SWITCH(TOGGLE_SWITCH),
.hour_alarm(hour_alarm),
.hour_time(hour_time),
.minute_alarm(minute_alarm),
.minute_time(minute_time),
.second_alarm(second_alarm),
.second_time(second_time)
);
//input?SET_TIME,//設(shè)置時間，高有效
//input?SET_ALARM,//設(shè)置鬧鈴時間，高有效
//input?HRS,//設(shè)置小時，高有效
//input?MINS,//設(shè)置分鐘，高有效
//input?TOGGLE_SWITCH,//打開、關(guān)閉報時控制，高有效
initial????????????????????????????????????????????????
begin????
RST=0;??????????????????????????????????????????????
HRS=0;//
MINS=0;//
SET_ALARM=0;//
SET_TIME=0;//
TOGGLE_SWITCH=1;//
#100;
RST=1;
#100;
SET_TIME=1;//設(shè)置時間，高有效
#10;
SET_TIME=0;
#40;
HRS=1;//設(shè)置小時，高有效
#10;
HRS=0;
#40;
HRS=1;//設(shè)置小時，高有效
#10;
HRS=0;
#40;
MINS=1;//設(shè)置分鐘，高有效
#10;
MINS=0;
#40;
MINS=1;//設(shè)置分鐘，高有效
#10;
MINS=0;
#40;
MINS=1;//設(shè)置分鐘，高有效
#10;
MINS=0;
#40;
SET_TIME=1;//設(shè)置時間完成
#10;
SET_TIME=0;
#40;
#1000;
SET_ALARM=1;//設(shè)置鬧鈴時間，高有效
#10;
SET_ALARM=0;
#40;
HRS=1;//設(shè)置小時，高有效
#10;
HRS=0;
#40;

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=541