uart串行通信接收接口(LED)Verilog代碼Quartus仿真

名稱：uart串行通信接收接口(LED)Verilog代碼Quartus仿真

軟件：Quartus

語言：Verilog

代碼功能：

uart串行通信接收接口(LED)

基本要求:掌握RS232串口的協(xié)議,運(yùn)用DE2的串口進(jìn)行接收PC的數(shù)據(jù)。波特率為9600,8位數(shù)據(jù)位,無奇偶校驗(yàn),一個(gè)停止位。

硬件驗(yàn)證要求:在PC機(jī)通過“調(diào)試助手”軟件發(fā)送數(shù)據(jù),DE2通過串口串行通信接收數(shù)據(jù),完成接收數(shù)據(jù)后在LED上面進(jìn)行顯示。

在完成基本要求的基礎(chǔ)上,可以通過撥碼開關(guān)來選擇奇偶校驗(yàn)的類別。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計(jì)文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. 管腳分配

5. Testbench

6. 仿真圖

部分代碼展示:

//UART串口接收
module?uart_recv(
????input??sys_clk,??????????????????//系統(tǒng)時(shí)鐘
????input?????????????sys_rst_n,????????????????//系統(tǒng)復(fù)位，低電平有效
input?????????????sw,???????????????????????//奇偶校驗(yàn)控制切換
????output????????????parity_errors,????????????//校驗(yàn)錯(cuò)誤指示
????input?????????????uart_rxd,?????????????????//UART接收端口
????output??reg???????uart_done,????????????????//接收一幀數(shù)據(jù)完成標(biāo)志信號(hào)
????output??reg?[7:0]?uart_data?????????????????//接收的數(shù)據(jù)
????);
????
//波特率9600
localparam?BPS_CNT??=?5208;????????//為得到指定波特率，50000000/9600=系統(tǒng)時(shí)鐘頻率/串口波特=5208
????????????????????????????????????????????????//需要對(duì)系統(tǒng)時(shí)鐘計(jì)數(shù)BPS_CNT次
//reg?define
reg????????uart_rxd_d0;
reg????????uart_rxd_d1;
reg?[15:0]?clk_cnt;?????????????????????????????//系統(tǒng)時(shí)鐘計(jì)數(shù)器
reg?[?3:0]?rx_cnt;??????????????????????????????//接收數(shù)據(jù)計(jì)數(shù)器
reg????????rx_flag;?????????????????????????????//接收過程標(biāo)志信號(hào)
reg?[?7:0]?rxdata;??????????????????????????????//接收數(shù)據(jù)寄存器
//wire?define
wire???????start_flag;
//*****************************************************
//**????????????????????main?code
//*****************************************************
//捕獲接收端口下降沿(起始位)，得到一個(gè)時(shí)鐘周期的脈沖信號(hào)
assign??start_flag?=?uart_rxd_d1?&?(~uart_rxd_d0);????
&&(clk_cnt?==?BPS_CNT/2))
????????????rx_flag?<=?1'b0;????????????????????//計(jì)數(shù)到停止位中間時(shí)，停止接收過程
????????else
????????????rx_flag?<=?rx_flag;
????end
end
//進(jìn)入接收過程后，啟動(dòng)系統(tǒng)時(shí)鐘計(jì)數(shù)器與接收數(shù)據(jù)計(jì)數(shù)器
always?@(posedge?sys_clk?or?negedge?sys_rst_n)?begin?????????
????if?(!sys_rst_n)?begin?????????????????????????????
????????clk_cnt?<=?16'd0;??????????????????????????????????
????????rx_cnt??<=?4'd0;
????end??????????????????????????????????????????????????????
????else?if?(?rx_flag?)?begin???????????????????//處于接收過程
????????????if?(clk_cnt?<?BPS_CNT?-?1)?begin
????????????????clk_cnt?<=?clk_cnt?+?1'b1;
????????????????rx_cnt??<=?rx_cnt;
????????????end
????????????else?begin
????????????????clk_cnt?<=?16'd0;???????????????//對(duì)系統(tǒng)時(shí)鐘計(jì)數(shù)達(dá)一個(gè)波特率周期后清零
????????????????rx_cnt??<=?rx_cnt?+?1'b1;???????//此時(shí)接收數(shù)據(jù)計(jì)數(shù)器加1
????????????end
????????end
????????else?begin??????????????????????????????//接收過程結(jié)束，計(jì)數(shù)器清零
????????????clk_cnt?<=?16'd0;
????????????rx_cnt??<=?4'd0;
????????end
end
reg?verify_bit=0;//校驗(yàn)
//根據(jù)接收數(shù)據(jù)計(jì)數(shù)器來寄存uart接收端口數(shù)據(jù)
always?@(posedge?sys_clk?or?negedge?sys_rst_n)?begin?
????if?(?!sys_rst_n)??
????????rxdata?<=?7'd0;?????????????????????????????????????
????else?if(rx_flag)????????????????????????????//系統(tǒng)處于接收過程
????????if?(clk_cnt?==?BPS_CNT/2)?begin?????????//判斷系統(tǒng)時(shí)鐘計(jì)數(shù)器計(jì)數(shù)到數(shù)據(jù)位中間
????????????case?(?rx_cnt?)
?????????????4'd1?:?rxdata[0]?<=?uart_rxd_d1;???//寄存數(shù)據(jù)位最低位
?????????????4'd2?:?rxdata[1]?<=?uart_rxd_d1;
?????????????4'd3?:?rxdata[2]?<=?uart_rxd_d1;
?????????????4'd4?:?rxdata[3]?<=?uart_rxd_d1;
?????????????4'd5?:?rxdata[4]?<=?uart_rxd_d1;
?????????????4'd6?:?rxdata[5]?<=?uart_rxd_d1;
?????????????4'd7?:?rxdata[6]?<=?uart_rxd_d1;
?4'd8?:?rxdata[7]?<=?uart_rxd_d1;
?????????????4'd9?:?verify_bit?<=?uart_rxd_d1;???//寄存數(shù)據(jù)位最高位
?????????????default:;????????????????????????????????????
????????????endcase
????????end
????????else?
????????????rxdata?<=?rxdata;
????else
????????rxdata?<=?7'd0;
end
//數(shù)據(jù)接收完畢后給出標(biāo)志信號(hào)并寄存輸出接收到的數(shù)據(jù)
reg?verify_led=0;
assign?parity_errors=verify_led;
always?@(posedge?sys_clk?or?negedge?sys_rst_n)?begin????????
????if?(!sys_rst_n)?begin
????????uart_data?<=?7'd0;???????????????????????????????
????????uart_done?<=?1'b0;
??verify_led<=0;
????end
????else?if(rx_cnt?==?4'd10)?begin???????????????//接收數(shù)據(jù)計(jì)數(shù)器計(jì)數(shù)到停止位時(shí)?
if(sw==1'b1)?//奇偶校驗(yàn)控制
??if(verify_bit!=^rxdata)begin?
??uart_data?<=?rxdata;????????????????????//寄存輸出接收到的數(shù)據(jù)
??uart_done?<=?1'b1;??????????????????????//并將接收完成標(biāo)志位拉高
??verify_led<=0;
?????end
??else?begin
??uart_data?<=?rxdata;???????????????????????????????????
??uart_done?<=?1'b0;?
??verify_led<=1;//檢驗(yàn)錯(cuò)誤led燈亮??
??end
else?//奇偶校驗(yàn)控制切換
??if(verify_bit==^rxdata)begin?
??uart_data?<=?rxdata;????????????????????//寄存輸出接收到的數(shù)據(jù)
??uart_done?<=?1'b1;??????????????????????//并將接收完成標(biāo)志位拉高
??verify_led<=0;
?????end
??else?begin
??uart_data?<=?rxdata;???????????????????????????????????
??uart_done?<=?1'b0;?
???????????verify_led<=1;//檢驗(yàn)錯(cuò)誤led燈亮??
??end
????end
????else?begin
????????uart_data?<=?uart_data;???????????????????????????????????
????????uart_done?<=?1'b0;?
????end????
end
endmodule

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=437