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名稱：幸運(yùn)老虎機(jī)VHDL游戲DE2-115開發(fā)板（代碼在文末下載）

軟件：Quartus II

語言：VHDL

代碼功能：

幸運(yùn)老虎機(jī)是游戲廳里最簡單的游戲之一,拉下幸運(yùn)老虎機(jī)的拉桿,3個輪盤就會開始旋轉(zhuǎn),如果3個輪盤的指針都指向同一個圖案時,就會得到獎勵。

本題目設(shè)計一個基于FPGA 的幸運(yùn)老虎機(jī)。

設(shè)計要求

系統(tǒng)主要外設(shè):自恢復(fù)式按鍵2個(keyl、key2)、LED燈2個、系統(tǒng)時鐘(50MHz);
系統(tǒng)主要功能:設(shè)計一個游戲機(jī),用3位數(shù)碼管來代替老虎機(jī)的3個輪盤,用0-7的數(shù)字來代替老虎機(jī)輪盤上的不同圖案。按下key1,3個數(shù)碼管的數(shù)字開始循環(huán)顯示,再次按下key1,3個數(shù)碼管的數(shù)字停止循環(huán),當(dāng)顯示的3個數(shù)字相同時,游戲勝利。
*備注:要求三個數(shù)碼管數(shù)字循環(huán)的速度不同,停止時的延遲時間也要不同;游戲勝利時,LED1要閃爍提示;
有“作弊”功能, 來指示當(dāng)前是否開啟作弊模式。按下該功能按鍵,每次都能贏,可用LED2的狀態(tài)

要求.jpg

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

本代碼已在DE2-115開發(fā)板驗(yàn)證，開發(fā)板如下，其他開發(fā)板可以修改管腳適配：

演示視頻：

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
--老虎機(jī)游戲
ENTITY?tiger_game?IS
???PORT?(
??????clk_in??:?IN?STD_LOGIC;--50MHz
??????rst_n???:?IN?STD_LOGIC;--復(fù)位
??????key?????:?IN?STD_LOGIC;--輸入按鍵
SW0?????:?IN?STD_LOGIC;--作弊按鍵
LED2????:?OUT?STD_LOGIC;--作弊指示燈
??????HEX0????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管段選
??????HEX1????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管段選
??????HEX2????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管段選
??????BEEP????:?OUT?STD_LOGIC--贏了提示
???);
END?tiger_game;
ARCHITECTURE?behave?OF?tiger_game?IS
--按鍵控制
???COMPONENT?data_ctrl?IS
??????PORT?(
?????????clk_in??:?IN?STD_LOGIC;
?????????rst_n???:?IN?STD_LOGIC;
?????????key?????:?IN?STD_LOGIC;
???SW0?????:?IN?STD_LOGIC;--作弊按鍵
???LED2????:?OUT?STD_LOGIC;--作弊指示燈
?????????current_state?:?OUT?STD_LOGIC_VECTOR(2?DOWNTO?0);
?????????data_1??:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????data_2??:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????data_3??:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0)
??????);
???END?COMPONENT;
???
???----贏了提示
???COMPONENT?BEEP_ctrl?IS
??????PORT?(
?????????clk_in??:?IN?STD_LOGIC;
?????????rst_n???:?IN?STD_LOGIC;
?????????current_state?:?IN?STD_LOGIC_VECTOR(2?DOWNTO?0);
?????????data_1??:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????data_2??:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????data_3??:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????BEEP????:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
--數(shù)碼管顯示模塊
COMPONENT?display?IS
???PORT?(
??clk?????????:?IN?STD_LOGIC;
??
??data_1??:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);--數(shù)字1
??data_2????:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);--數(shù)字2
??data_3??:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);--數(shù)字3
??
??HEX0????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??HEX1????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??HEX2????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
???);
END?COMPONENT;
???
???
???SIGNAL?data_1????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?data_2????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?data_3????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?current_state?:?STD_LOGIC_VECTOR(2?DOWNTO?0);
BEGIN
--按鍵控制
???i_data_ctrl?:?data_ctrl
??????PORT?MAP?(
?????????clk_in?????????=>?clk_in,--50MHz
?????????rst_n??????????=>?rst_n,--復(fù)位
?????????key????????????=>?key,--輸入按鍵
???SW0????????????=>SW0?,--作弊按鍵
???LED2???????????=>LED2?,--作弊指示燈
?????????current_state??=>?current_state,--當(dāng)前狀態(tài)
?????????data_1?????????=>?data_1,--數(shù)字1
?????????data_2?????????=>?data_2,--數(shù)字2
?????????data_3?????????=>?data_3--數(shù)字3
??????);
???
???
???
--數(shù)碼管顯示模塊
???i_display?:?display
??????PORT?MAP?(
?????????clk?????=>?clk_in,
?????????data_1??=>?data_1,--數(shù)字1
?????????data_2??=>?data_2,--數(shù)字2
?????????data_3??=>?data_3,--數(shù)字3
?????????hex0????=>?HEX0,--數(shù)碼管段選
?????????hex1????=>?HEX1,--數(shù)碼管段選
?????????hex2????=>?HEX2--數(shù)碼管段選
??????);
???
???
???----贏了提示
???i_BEEP_ctrl?:?BEEP_ctrl
??????PORT?MAP?(
?????????clk_in?????????=>?clk_in,--50MH
?????????rst_n??????????=>?rst_n,--復(fù)位
?????????current_state??=>?current_state,--當(dāng)前狀態(tài)
?????????data_1?????????=>?data_1,--數(shù)字1
?????????data_2?????????=>?data_2,--數(shù)字2
?????????data_3?????????=>?data_3,--數(shù)字3
?????????BEEP???????????=>?BEEP?----贏了提示
??????);
???
END?behave;

設(shè)計文檔：

1.工程文件