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名稱：籃球計(jì)時器倒計(jì)時器DE0-CV開發(fā)板籃球比賽定時器（代碼在文末下載）

軟件：Quartus II

語言：VHDL

代碼功能：

籃球計(jì)時器倒計(jì)時器要求籃球比賽：

(1)主持人宣布比賽開始前,所有模塊就位。

(2)裁判宣布開始時,比賽正式開始,進(jìn)入12分鐘倒計(jì)時,同時進(jìn)入24秒倒計(jì)時搶球,且信號燈顯示搶到球的一方。

(3)當(dāng)球被另方奪取時,重新進(jìn)入24秒倒計(jì)時,信號燈顯示搶到球的一方。

(4)當(dāng)24秒倒計(jì)時為0時(犯規(guī)時),蜂嗚器(信號燈)提示。

(5)當(dāng)裁判宣布暫停吋,12分鐘倒計(jì)吋暫停,24秒倒計(jì)時復(fù)位,進(jìn)人60秒倒計(jì)時。60秒倒計(jì)時為0時,暫停結(jié)束,蜂鳴器(信號燈)提示,繼續(xù)12分鐘倒計(jì)時。

(6)一節(jié)比賽結(jié)束時,蜂鳴器(信號燈)提示,數(shù)碼管顯示節(jié)數(shù)。

本代碼已在DE0-CV開發(fā)板驗(yàn)證，開發(fā)板如下，其他開發(fā)板可通過修改管腳適配：

演示視頻：

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--控制模塊
ENTITY?control?IS
???PORT?(
??????clk????????????:?IN?STD_LOGIC;--時鐘
??????reset??????????:?IN?STD_LOGIC;--復(fù)位
??????clk_1??????????:?IN?STD_LOGIC;--1hz
??????start_n????????:?IN?STD_LOGIC;--開始
??????stop_n?????????:?IN?STD_LOGIC;--暫停
??????ball_sw1???????:?IN?STD_LOGIC;--搶球1
??????ball_sw2???????:?IN?STD_LOGIC;--搶球2
??????stop_led???????:?OUT?STD_LOGIC;--暫停指示燈
??????over24sec_led??:?OUT?STD_LOGIC;--24s超時指示燈
??????ball_led???????:?OUT?STD_LOGIC_VECTOR(1?DOWNTO?0);--搶球指示燈
??????end_led????????:?OUT?STD_LOGIC;--結(jié)束指示燈
??????match??????????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);--比賽節(jié)數(shù)
??????timedown_o?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--倒計(jì)時
??????time12_min_o???:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--12分鐘分
??????time12_sec_o???:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--12分鐘秒
???);
END?control;
ARCHITECTURE?trans?OF?control?IS
???type?state_type?is?(s_idle,s_wait12min,s_stop,s_over24sec,s_end,s_start);
???signal?state?:?state_type;
???SIGNAL?ball_sw1_buf0?:?STD_LOGIC;
???SIGNAL?ball_sw1_buf1?:?STD_LOGIC;
???SIGNAL?ball_sw2_buf0?:?STD_LOGIC;
???SIGNAL?ball_sw2_buf1?:?STD_LOGIC;
???SIGNAL?sw1_r?????????:?STD_LOGIC;
???SIGNAL?sw2_r?????????:?STD_LOGIC;
???SIGNAL?time24????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?time60????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?time12_min????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?time12_sec????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?match_num?????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";
???
???
BEGIN
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????ball_sw1_buf0?<=?ball_sw1;--搶球1
?????????ball_sw1_buf1?<=?ball_sw1_buf0;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clk)
???BEGIN
??????IF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????ball_sw2_buf0?<=?ball_sw2;--搶球2
?????????ball_sw2_buf1?<=?ball_sw2_buf0;
??????END?IF;
???END?PROCESS;
???
???sw1_r?<=?NOT(ball_sw1_buf0)?AND?ball_sw1_buf1;--搶球1
???sw2_r?<=?NOT(ball_sw2_buf0)?AND?ball_sw2_buf1;--搶球2
???
???timedown_o?<=?time60?WHEN?(state?=?s_stop)?ELSE--根據(jù)狀態(tài)切換顯示60s還是24s倒計(jì)時
?????????????????time24;
???time12_min_o?<=?time12_min;--分鐘倒計(jì)時
???time12_sec_o?<=?time12_sec;--秒鐘倒計(jì)時
???
???PROCESS?(clk,?reset)
???BEGIN
??????IF?((NOT(reset))?=?'1')?THEN
?????????time60?<=?"00111100";--復(fù)位
??????ELSIF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(state?=?s_wait12min?AND?stop_n?=?'0')?THEN
????????????time60?<=?"00111100";--60s
?????????ELSIF?(state?=?s_stop?AND?clk_1?=?'1')?THEN
????????????time60?<=?time60?-?"00000001";--倒計(jì)時
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???--24秒倒計(jì)時
???PROCESS?(clk,?reset)
???BEGIN
??????IF?((NOT(reset))?=?'1')?THEN
?????????time24?<=?"00011000";
??????ELSIF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(sw1_r?=?'1'?OR?sw2_r?=?'1'?OR?start_n?=?'0')?THEN
????????????time24?<=?"00011000";
?????????ELSIF?(state?=?s_stop)?THEN
????????????time24?<=?"00011000";
?????????ELSIF?(state?=?s_wait12min?AND?clk_1?=?'1')?THEN
????????????time24?<=?time24?-?"00000001";
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???--12分鐘倒計(jì)時
???PROCESS?(clk,?reset)
???BEGIN
??????IF?((NOT(reset))?=?'1')?THEN
?????????time12_min?<=?"00000000";
?????????time12_sec?<=?"00000000";
??????ELSIF?(clk'EVENT?AND?clk?=?'1')?THEN
?????????IF?(state?=?s_start)?THEN

設(shè)計(jì)文檔：

1. 工程文件