Quartus數(shù)字頻率計(jì)VHDL代碼

名稱：Quartus數(shù)字頻率計(jì)VHDL代碼

軟件：Quartus

語言：VHDL

代碼功能：

課題內(nèi)容及要求：

本課題采用Intl公司(原 Altera) CycloneⅢ系列的EP3C8O或EP3C40型FPGA芯片,利用 LTE-SOPO-02FD型EDA/SOPC實(shí)驗(yàn)開發(fā)平臺(tái)的資源,根據(jù)等精度測頻原理,設(shè)計(jì)一個(gè)數(shù)字頻率計(jì),對脈沖進(jìn)行頻率測量,測得結(jié)果在數(shù)碼管上顯示,并設(shè)計(jì)相應(yīng)的功能按鍵,能夠在所測量的整個(gè)頻段內(nèi)部,均可實(shí)現(xiàn)相同精度的測量,即測量精度與頻率無關(guān)。

按鍵功能包括(1)閘門按鍵(01S,1S和105)、(2)手動(dòng)測量、(3)自動(dòng)測量,在數(shù)碼管上顯示閘門檔位擴(kuò)展內(nèi)容:16*16點(diǎn)陣顯示學(xué)號和姓名。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

1. 工程文件

2. 程序文件

3. 程序編譯

4. 管腳分配

5. RTL圖

6. Testbench

7. 仿真圖

整體仿真圖

閘門模塊仿真

頻率計(jì)算模塊

顯示模塊

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
--頻率計(jì)算模塊
ENTITY?frequency_calculate?IS
???PORT?(
??????clk_in???????????:?IN?STD_LOGIC;--輸入50M基準(zhǔn)時(shí)鐘
??????reset_p??????????:?IN?STD_LOGIC;--復(fù)位信號
??????signal_in????????:?IN?STD_LOGIC;--待測頻率輸入
??????doors_open???????:?IN?STD_LOGIC;--閘門
??????total_frequency??:?OUT?INTEGER--輸出頻率
???);
END?frequency_calculate;
ARCHITECTURE?behave?OF?frequency_calculate?IS
???SIGNAL?door_1s?????????:?STD_LOGIC;
???SIGNAL?CNT1????????????:?INTEGER?:=?10;--基準(zhǔn)時(shí)鐘計(jì)數(shù)器
???SIGNAL?CNT2????????????:?INTEGER?:=?10;--待測頻率計(jì)數(shù)器
???SIGNAL?CNT1_buf????????:?INTEGER?:=?10;--基準(zhǔn)時(shí)鐘計(jì)數(shù)器寄存器
???SIGNAL?CNT2_buf????????:?INTEGER?:=?10;--待測頻率計(jì)數(shù)器寄存器
???SIGNAL?CNT1_bufc???????:?INTEGER?:=?10;--基準(zhǔn)時(shí)鐘計(jì)數(shù)器寄存器
???SIGNAL?CNT2_bufc???????:?INTEGER?:=?10;--待測頻率計(jì)數(shù)器寄存器
SIGNAL?total_frequency_int???????:?INTEGER?:=?10;
???SIGNAL?door_1s_buf?????:?STD_LOGIC?:=?'0';
???SIGNAL?door_1s_negedge?:?STD_LOGIC;
BEGIN
????
???PROCESS?(signal_in)
???BEGIN
??????IF?(signal_in'EVENT?AND?signal_in?=?'1')?THEN
?????????door_1s<=?doors_open;--閘門信號同步到signal_in信號下
??????END?IF;
???END?PROCESS;
???PROCESS?(clk_in)
???BEGIN
??????IF?(clk_in'EVENT?AND?clk_in?=?'1')?THEN
?????????IF?(door_1s?=?'1')?THEN
????????????CNT1?<=?CNT1?+?1;--基準(zhǔn)時(shí)鐘計(jì)數(shù)器
?????????ELSE
????????????CNT1?<=?0;
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(signal_in)
???BEGIN
??????IF?(signal_in'EVENT?AND?signal_in?=?'1')?THEN
?????????IF?(door_1s?=?'1')?THEN
????????????CNT2?<=?CNT2?+?1;--待測頻率計(jì)數(shù)器
?????????ELSE
????????????CNT2?<=?0;
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???PROCESS?(clk_in)
???BEGIN
??????IF?(clk_in'EVENT?AND?clk_in?=?'1')?THEN
?????????door_1s_buf?<=?door_1s;
??????END?IF;
???END?PROCESS;
???
???door_1s_negedge?<=?NOT(door_1s)?AND?door_1s_buf;--閘門信號下降沿
???PROCESS?(clk_in)
???BEGIN
??????IF?(clk_in'EVENT?AND?clk_in?=?'1')?THEN
?????????CNT1_buf?<=?CNT1;--基準(zhǔn)頻率計(jì)數(shù)
?????????CNT2_buf?<=?CNT2;--待測頻率計(jì)數(shù)
??????END?IF;
???END?PROCESS;
???
???
???PROCESS?(clk_in)
???BEGIN
??????IF?(clk_in'EVENT?AND?clk_in?=?'1')?THEN
?????????IF?(door_1s_negedge?=?'1')?THEN
????????????CNT1_bufc?<=?CNT1_buf;--基準(zhǔn)頻率計(jì)數(shù)
????????????CNT2_bufc?<=?CNT2_buf;--待測頻率計(jì)數(shù)
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???--待測頻率計(jì)算=CNT2_buf*5*10^7/CNT1_buf
???total_frequency?<=?(50000000?/?CNT1_bufc)?*?CNT2_bufc;--單位Hz
???
END?behave;

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=422